Semiconductor memory device and driving method thereof

ABSTRACT

A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a calibration controller for controlling the predetermined delay time of the variable delay in response to output AC parameters.

FIELD OF THE INVENTION

The present invention relates to a semiconductor memory device, and moreparticularly, to a synchronous semiconductor device and a method forcontrolling output AC parameters thereof.

DESCRIPTION OF RELATED ART

A synchronous semiconductor memory device shares a system clock outputfrom a clock generator with a chipset and receives or transfers command,address and data in synchronization with the system clack.

FIG. 1 is a block diagram of a communication scheme between asynchronous dynamic random access memory (DRAM) and a chipset.

In a write operation, the chipset transfers command CMD, address ADD,and data DQ to the DRAM. The chipset also transfers a data strobe signalDQS to the DRAM together with the data DQ.

In a read operation, the DRAM receives the command CMD and the addressADD from the chipset and transfers the corresponding data DQ to thechipset together with the data strobe signal DQS.

The chipset transfers the data strobe signal DQS to the DRAM in thewrite operation, while the DRAM transfers the data strobe signal DQS tothe chipset in the read operation.

The data strobe signal DQS is used for source synchronization and isalso called “echo clock”. If the data DQS is strobed in synchronizationwith the data strobe signal DQS, skew between the clock CLK and the dataDQS can be reduced.

FIG. 2 is a diagram relating AC parameters in a read operation of a DDRSDRAM.

Timing of data DQ and data strobe signal DQS is illustrated in FIG. 2.In FIG. 2, “tDQSQ” is a parameter representing skew between the datastrobe signal DQS and the data DQ, “tDQSCK” is a parameter representingskew between the data strobe signal DQS and clock CLK, and “tAC” is aparameter representing skew between the data DQ and the clock CLK.

In order to enable a chipset to receive the data DQ, a DRAM sets thedata strobe signal DQS to a low-Z state during tRPRE (read DQS preambletime). When data (DQ) transmission is completed, the DRAM sets the datastrobe signal DQS to a high-Z state after tRPST (read DQS postambletime). In this manner, the read operation is completed.

If any one of the above-described parameters does not meet thespecification, operation error will occur because the chipset receivesincorrect data. However, the conventional DRAM module and chipset do notactively control the output AC parameters, e.g., tDQSQ, tDQSCK, etc.Thus, the system will shut down when the output AC parameters aredistorted by fluctuation of a board power supply or ambient temperaturecharacteristic. Moreover, as the operation speed of the DRAM increases,the specification requirements of the output AC parameters becomenarrower. Consequently, the development of high-speed DRAMs becomesincreasingly more difficult.

SUMMARY OF THE INVENTION

It is, therefore, an object of the present invention to provide asemiconductor memory device that can actively control the output ACparameters, and a driving method thereof.

In accordance with an aspect of the present invention, a semiconductormemory device includes: a variable delay for delaying a delay lockedloop (DLL) clock by a predetermined delay time to output a delayed DLLclock; an output driver for outputting data and data strobe signal inresponse to the delayed DLL clock; and a calibration controller forcontrolling the predetermined delay time of the variable delay inresponse to output AC parameters.

In accordance with another aspect of the present invention, a method fordriving a semiconductor memory device includes: measuring output ACparameters; setting a delay value with respect to a delay locked loop(DLL) clock in response to the measured values of the output ACparameters; delaying the DLL clock by the delay value to output adelayed DLL clock; and outputting data strobe signal and data havingcalibrated output AC parameters in response to the delayed DLL clock.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and features of the present invention willbecome apparent from the following description of the preferredembodiments given in conjunction with the accompanying drawings, inwhich:

FIG. 1 is a block diagram of a communication scheme between aSynchronous DRAM and a chipset;

FIG. 2 is a diagram relating AC parameters in a read operation of a DDRSDRAM;

FIG. 3 is a block diagram of a DRAM in accordance with a firstembodiment of the present invention;

FIG. 4 is a flow chart of a calibration operation of the DRAM of FIG. 3;

FIG. 5 is a block diagram of a DRAM in accordance with a secondembodiment of the present invention; and

FIG. 6 is a block diagram of a DRAM in accordance with a thirdembodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

A semiconductor memory device and a driving method thereof in accordancewith exemplary embodiments of the present invention will be described indetail with reference to the accompanying drawings.

FIG. 3 is a block diagram of a DRAM in accordance with a firstembodiment of the present invention.

The DRAM in accordance with the first embodiment of the presentinvention includes a variable delay 30, a pre-driver 32, a main driver34, and a calibration controller 36. The variable delay 30 delays adelay locked loop (DLL) clock DLL_CLK to output a delayed DLL clockDLL_CLKD, and the pre-driver 32 pre-drives an output data signal inresponse to the delayed DLL clock DLL_CLKD. The main driver 34 drives adata output terminal DQ in response to an output signal of thepre-driver 32. The calibration controller 36 controls a delay time(τ_(d)) of the variable delay 30 in response to measured values ofoutput AC parameters. The measured values of the output AC parametersare received from a chipset.

FIG. 4 is a flow chart of a calibration operation of the DRAM of FIG. 3.

When the chipset inputs a calibration command to the DRAM in step S10,the DRAM transfers data strobe signal DQS and data DQ to the chipset instep S12.

In step S14, the chipset measures the output AC parameters (e.g.,tDQSCK, tDQSQ, etc.) in the data strobe signal DQS and the data DQ, andtransfers the measured values of the output AC parameters to the DRAM.In step S16, the calibration controller 36 sets the delay time (τ_(d))of the variable delay 30 in response to the measured values.

In this case, the variable delay 30 delays the DLL clock DLL_CLK by+τ_(d) or −τ_(d), and the pre-driver 32 is driven in response to thedelayed DLL clock DLL_CLKD in step S18. In step S20, the calibrated datastrobe signal DQS and the calibrated data DQ are transferred to thechipset.

In step S22, the chipset remeasures the output AC parameters, based onthe calibrated data strobe signal DQS and the calibrated data DQ, anddetermines if the AC parameters comply with the specification. When theAC parameters comply with the specification, the calibration operationis completed. When the AC parameters do not comply with thespecification, the process returns to step S14 to transfer theremeasured values to the DRAM. This loop is repeated until the ACparameters comply with the specification. Since steps subsequent to stepS22 are a verify operation, they can be omitted.

FIG. 5 is a block diagram of a DRAM in accordance with a secondembodiment of the present invention.

The DRAM in accordance with the second embodiment of the presentinvention includes a variable delay 50, a pre-driver 52, a main driver54, a feedback input buffer 56, and a timing measurer 58. The variabledelay 50 delays a DLL clock DLL_CLK to output a delayed DLL clockDLL_CLKD, and the pre-driver 52 pre-drives an output data signal inresponse to the delayed DLL clock DLL_CLKD. The main driver 54 drives adata output terminal DQ in response to an output signal of thepre-driver 52. The feedback input buffer 56 feeds back data DQ and datastrobe signal DQS to the timing measurer 58 in response to a calibrationtest mode signal TM_CAL. The timing measurer 58 measures output ACparameters (e.g., tDQSCK, tDQSQ, etc.) of the data DQ and the datastrobe signal DQS, and controls the delay time (τ_(d)) of the variabledelay 30 in response to the measurement values of the output ACparameters.

When a calibration command is input from the chipset, the DRAM activatesthe calibration test mode signal TM_CAL in response to the calibrationcommand. When the calibration test mode signal TM_CAL is activated, thefeedback input buffer 56 is enabled to receive the data DQ and the datastrobe signal DQS. The timing measurer 58 measures skew between the dataDQ and the data strobe signal DQS and controls the delay time (τ_(d)) ofthe DLL clock DLL_CLK according to the measured skew. When thecalibration test mode signal TM_CAL is deactivated after the calibrationoperation is completed, the DRAM transfers a calibration test mode exitsignal to the chipset.

FIG. 6 is a block diagram of a DRAM in accordance with a thirdembodiment of the present invention.

The DRAM in accordance with the third embodiment of the presentinvention includes a variable delay 60, a pre-driver 62, a main driver64, a real-time monitoring buffer 66, and a timing measurer 68. Thevariable delay 60 delays a DLL clock DLL_CLK to output a delayed DLLclock DLL_CLKD, and the pre-driver 62 pre-drives an output data signalin response to the delayed DLL clock DLL_CLKD. The main driver 64 drivesa data output terminal DQ in response to an output signal of thepre-driver 62. The real-time monitoring buffer 66 monitors data

DQ and data strobe signal DQS, which is being transferred to thechipset. The timing measurer 68 measures output AC parameters (e.g.,tDQSCK, tDQSQ, etc.) in data DQ and data strobe signal DQS received fromthe real-time monitoring buffer 66, and controls the delay time (τ_(d))of the variable delay 60 in response to the measured values.

In this embodiment, the DRAM itself performs the calibration withoutcalibration command provided from the chip set. Although the real-timemonitoring buffer 66 must be embedded into the DRAM, it is possible toomit time taken to perform the calibration through the communicationbetween the DRAM and the chipset.

If undesired skew occurs during the operation of the DRAM, the skew canbe immediately adjusted to meet the specification without time lossbecause the DRAM monitors the skew in real time.

As described above, the embodiments of the present invention provide thetiming control methods that can actively adjust the output AC parametersin the memory device. In the first method, the chipset transfers thecalibration command and the measured values of the output AC parametersto the memory device, and the memory device performs the calibrationoperation. In the second method, when the chipset transfers thecalibration command to the memory device, the memory device measures theoutput AC parameters and performs the calibration operation. In thethird method, the memory device transfers the data strobe signal DQS andthe data DQ to the chipset while monitoring them in real time, withoutcalibration command of the chipset.

Therefore, the memory device can actively control the output ACparameters, thus providing the decreased failure rate and the improvedreliability. In addition, the memory device can cope with the narrowedspecification requirements of the AC parameters, attributing to thedevelopments of high-speed memory devices.

Although the DRAM has been described, the present invention is notlimited to the DRAM. That is, the present invention can also be appliedto any memory device that communicates the chipset using data strobesignal.

The present application contains subject matter related to Korean patentapplication No. 2006-59735, filed in the Korean Intellectual PropertyOffice on Jun. 29, 2006, the entire contents of which are incorporatedherein by reference.

While the present invention has been described with respect to certainpreferred embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the scope of the invention as defined in the following claims.

What is claimed is:
 1. A memory system, comprising: a variable delayconfigured to delay a clock; an output driver configured to transferdata to a chipset in response to a calibration command received from thechipset and the delayed clock; an output buffer configured to transfer adata strobe signal to the chipset in response to the calibration commandand the clock; and a calibration controller configured to control thedelay time of the variable delay according to an output AC parametermeasured by the chipset.